The present invention relates to a memory access control system for use in a data processing system and, more particularly, to an internal processing system for a memory access control unit, connected to arithmetic processors, input/output processors and a main memory unit, for centralized management and processing of memory access requests from the processors. The memory access control unit here may be one having a large-capacity cache memory of either a store-in or a store-through type.
The above-mentioned memory access control system, also known as a system control unit, is required to impartially and efficiently process memory access requests from a plurality of requesters. If it has a cache memory within, such operations as discrimination between a cache hit and a cache miss and, in the case of a miss, the transfer of block data to and from the main memory may complicate its control logic.
U.S. Pat. No. 4,317,168 concerns a cache organization for data transfers for line fetch and line castout between a store-in type cache memory and a main memory unit. Though it somewhat differs from the present invention in that the presence of only one requester unit is tacitly presupposed, it is nevertheless true that efficient use of such a store-in type cache memory requires much ingenuity and a great deal of hardware. Thus, a line fetch or line castout invited by a cache miss, or competition on the same bank in an interleaved cache memory could disturb the pipeline and thereby complicate the control.
Such a disturbance of the pipeline could be even more serious in a memory access control unit which has to accept accesses from a plurality of requesters. Besides simple cache misses, there occur diverse competitions--those between cache memory banks, between set addresses in a set-associative type cache memory, between cache-missing requests for main memory access, and between line fetch/castout processing and the following cache hit processing--within such a unit, and they all can disturb the pipeline. Where there are a plurality of requesters, even if any of such competitions occurs, other requests than the competing ones have to be processed without delay. On the other hand, any request whose processing is held up by a cache miss or competition should be prevented from being outrun by any subsequent request from the same requester.
Usually, in such cases as the above-mentioned where processing cannot be achieved in a pipeline flow, the request or memory access concerned is led out of the pipeline, and processed after being kept waiting in a buffer or a queue provided particularly for each case. During this wait, the processing of subsequent requests from the same requester should be prohibited. These pipeline disturbing factors necessitate a number of buffers and a circuit to control them or the overall flow of requests, resulting in a great deal of complex hardware.